The present invention relates to a path test system for an ATM switch.
Of recent years ATM (Asynchronous Transfer Mode) has been studied actively as a technique for a switching unit for a broadband integrated services digital network (BISDN) that is the next generation of ISDN.
The switch facilities of an ATM switching unit are equipped with a hardware configuration for high-speed operation. Thus, it is difficult to monitor directly the internal operation of the ATM switch. For this reason, the development of a method of performing a test to determine if the switch functions properly has been expected.
FIG. 1 illustrates a prior art. In this figure, 1 denotes a test cell inserting section, 2 denotes a test cell generating section, 3 denotes an ATM switch (ATMSW), 4 denotes a test cell extracting section, and 5 denotes a test cell decision section.
The ATM switch 3 in an ATM exchange has a function of switching a cell comprised of a 5-byte header and a 48-byte information field in accordance with header information (VPI/VCI: virtual path identifier /virtual channel identifier) and transferring it to an output (transmission line) determined by the header. In this case, knowing whether the ATM switch performs a switching operation properly in accordance with the header information is very important for maintaining the quality (performance) of the switching unit and moreover it is essential for maintenance thereof.
Here, a conventional method of checking the ATM switch will be described with reference to FIG. 1. The test cell generating section 2 is associated with the cell inserting section 1 provided on a cell transmission line input to the ATM switch. In testing the ATM switch the test cell generating section 2 generates a cell having a specific value (for example, all zeros) as its VCI and predetermined contents as the contents of its information field. This cell is inserted between usual cells for communication in the cell inserting section 1, and entered into the ATM switch 3 over the transmission line.
The ATM switch 3 establishes a path corresponding to the VCI having the specific value allocated to the test cell so as to transfer the test cell to a predetermined outgoing transmission line. If, therefore, the ATM switch 3 operates properly, the test cell will be output onto a predetermined transmission line. The test cell extracting section 4, provided on a transmission line onto which the test cell is output, extracts the test cell having the specific VCI value and outputs it to the test cell decision section 5.
The test cell decision section 5 checks the test cell extracted by the test cell extracting section 4 with the test cell generated by the test cell generating section 2. If the test cell extracted is identified as the test cell generated, then the decision section 5 outputs the test result representing the normality of the ATM switch 3.
A problem with the prior art system is that when, in the test cell decision section 5, by receiving data of a specific information field set in advance as a test cell from the test cell generating section 2 which does not agree with a cell extracted by the extracting section 4, it becomes impossible to detect whether or not the ATM switch 3 can switch all cells properly. That is, a test of the ATM switch (ATMSW) 3 has required an advance transmission of data in the information field of a test cell from the test cell generating section 2 on the input side of the switch to the test cell decision section 5 on the output side, which takes additional test time.
In addition, since the contents of the information field contained in a test cell are fixed, a problem arises in that variations in a bit pattern caused by a hardware fault occurring on a switch path cannot necessarily be detected. That is, if the contents of the information field in a test cell are fixed, it is impossible to detect the occurrence of a fault which causes a variation in a bit pattern corresponding to the information field pattern of the test cell. For example, when the content of the information field in the test cell is fixed to all zeros, the occurrence of a fault in which a line is stuck to "O" can not be detected.